• The reduction of cost and power consumption of 100Gb/s transmission equipment.
• The need of future-proof component technologies for next generation terabit networks.

Chips will be packaged and driven at 28 and then 56 GBauds to realize first PIC-to-PIC Terabit range transmissions. The innovation introduced by the monolithic integration of RX and TX with novel vector EAM-based sources should bring a real breakthrough in cost, size and consumption of Terabit components.

The specific objectives are:

• Demonstration and mastering of a monolithic integration technology of InP-based TX and RX chips suitable for handling 100Gb/s QPSK-type modulation formats.
• Demonstration of a future-proof approach by enhancing the bit rate to 200 Gb/s and providing concepts up to 400 Gb/s on a single fiber and wavelength.
• Module packaging of the TX and RX PICs with driving electronics.
• Demonstration of PIC to PIC transmission at 100 and 200 Gb/s.
• Simulations at the device and system levels to identify capabilities and limitations and to contribute to specifications.

The innovations claimed are:

• Small size TX chips suitable for multi-level coding (QPSK, QAM), based on phase switching in EAM-based PICs.
• Fully integrated RX chips demultiplexing both polarizations of the incoming light signal (DP-QPSK).
• Evaluation and prototype fabrication of novel monolithic coherent receiver types, applying multiport approaches.
• Demonstration of low-power low-footprint multi-level coding TX and RX.
• Coplanar coherent receiver package with gain-controlled linear electrical amplifiers.
• Demonstration of 200 – 400 Gb/s capability of InP-based TX and RX PICs.
• Integrated approach for photonic circuit numerical modelling and design.